The Virtual Interconnect Test(VIT) module generates patterns for testing boundary-scan nets using only the virtual access provided by boundary scan circuitry. VIT patterns provide 100% pin-level fault coverage for stuck-at pins, shorts, and opens.
On pure boundary-scan nets, VIT verifies that every device is operational at the pin level and that every interconnection – from silicon to lead bonds to solder bonds to the circuit board itself – is intact. VIT patterns can also verify the interconnections of an assembly's primary inputs and outputs, if physical test point access is available.
VIT Plus, a standard extension of the VIT module, supports in-circuit testing of assemblies that contain a mix of scan and non-scan logic. VIT Plus patterns provide 100% detection of shorts between boundary-scan nets and non-scan nets where only the non-scan nets have bed-of-nails access.
VIT and VIT Plus patterns are generated automatically from a circuit net list and the BSDL models of boundary-scan devices. VIT tests eliminate complex manual pattern generation, reduce the number of test pads required for detection of all structural faults, and simplify test hardware requirements.

VIT Features

• Detects stuck-at pin faults
• Tests Shorts/opens
• Tests for shorts between scan and non- scan nets
• Tests transparent components (i.e. Buffers, Resistors)
• Implements logical constraints
• Provides detailed fault coverage reports

Testing Transparent Series Components

The VIT module can automatically generate patterns that propagate through transparent series components such as series resistors and non-inverting buffers, to test the continuity of their interconnections. For example, when VIT recognizes that there is a resistor in series between a boundary scan driver and receiver, it generates patterns that correctly test both nets by passing signals from the driver through the resistor to the receiver. Based on the information in the net list, device characteristic models, and user switches in the process control menu, VIT software can automatically create an input file that identifies series components.

Defining Logical Constraints

VIt’s automatic pattern generator recognizes the logical constraints that users assign to the nets, leads, and tester pins involved in a VIT test.
A logical constraint specifies the value that VIT will apply or detect for the duration of a VIT test. When an assembly has a mix of scan and non-scan devices, logical constraints are commonly specified to drive a net to constant logic state or to expect an un driven net to remain at a constant logic state. This capability is used to disable or enable circuits that may be desirable or may interfere with a given test.

VIT Fault Coverage Report

The VIT module generates a fault coverage report to help test developers increase fault coverage on boards that have a mix of boundary scan and non-scan devices. In this report, all the nets on a DUT are sorted into six fault coverage classes. Each class defines the level of fault coverage that can be achieved using VIT, ranging from 100% fault coverage on pure boundary scan nets to zero fault coverage on non scan-nets where there is no physical access. Using this report, test engineers can quickly see where other test techniques can be applied to improve fault coverage.

Network classes recognized by VIT

• Class 1 - Pure scan nets.
• Class 2 - Partial scan nets that have at least one scan driver, one scan receiver, and one non-scan device lead.
• Class 3 - Nets where scan out-puts or tester channels drive non-scan inputs.
• Class 4 - Boundary-scan inputs connected to power or ground.
• Class 5 - Non-scan nets with no tester access.
• Class 6 - TAP nets.