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Features:
- High performance plug & play PCI based controller
- JPCI™ 32-bit (IEEE 1149.1) bus controller
- Fast throughput of up to 25 Mbits/sec
- 100 MHz system clock and up to 35 MHz programmable TCK rate
- Adaptive Clocking™ Technology
- 32 general purpose fully programmable parallel I/O channels
- 2 MB cache multi-page memory behind TDI/TDO
- Two 24 bit analog channels
- Performs non-compliant test access port (TAP) operations
- Meets addressable scan port (ASP) requirements
- Supports industry standard vector formats SVF, JAM/STAPL, IEEE
1532
- Programmable logic levels (1.8V to 5.0V)
- Configurable to service up to 16 individual scan chains or targets
JPCI test bus controller
JPCI™ is a proprietary 32-bit (IEEE1149.1) bus-master that
eliminates performance bottlenecks present in most commercial JTAG
controllers. In addition to TAP control circuitry, JPCI™ relies
on a built in PCI interface, Adaptive Clocking™ technology,
and multi-page memory backed TDI & TDO to facilitate high data
throughput to targets. Equipped with a 100 MHz system clock, JPCI’s
unique architecture eliminates transmission inefficiencies and provides
reliable, fast data transmission rates of up to 25 Megabits/sec
to targets without imposing physical proximity constraints. more...
Adaptive Clocking™ Technology
Adaptive Clocking™
enables operation of the JTAG port at high TCK rates, while eliminating
the effect of path delays between the controller and the target.
It mitigates instabilities and intermittencies caused by high-speed
operation. This proprietary technique compensates for path delays,
allowing the ScanMaster™ controller to operate at the maximum
TCK rate tolerated by target devices.
With the effects of path delay eliminated, and not requiring the
use of re-timing PODS, the ScanMaster™ controller can be located
an ergonomically suitable distance (up to 15 meters) away from the
target. This not only eliminates the adverse effects of PODS on
test/program reliability and repeatability, but also alleviates
space constraints PODs impose on production fixture set-ups. more
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32 fully programmable parallel I/O channels
ScanMaster has 32 fully programmable parallel I/O channels. These
channels are used under program control to disable conflicting devices
on the DUT, and toggle control circuitry of programmable parts such
as Flash memories. The logic levels on these channels can be set
to 3.3V or 5V.
2 MB multi-page cache memory behind TDI/TDO
In programming and test applications large sets of data flow through
TDI and TDO. Cache memory allocated to TDI and TDO allows smooth
flow of data to and from the target and prevents frequent interruptions.
Multi-page memory enables short read/write cycles between cache
memory and PCI bus controller, thus enabling JPCI™ to spend
minimal time performing memory related operations.
Analog Channels
ScanMaster’s™ unique analog channels can safeguard
the target by continuously monitoring user specified parameters
of the target to prevent possible damage during testing and/or device
programming:
- Pre-power up ‘shorts’ testing on power and ground
lines
- Monitoring board current draw
- General purpose analog measurement
- Analog measurements to detect manufacturing faults
ScanMaster™ operating environments
ScanNavigator RTE
features a comprehensive graphical user environment for ScanMaster
setup and runtime control. Through the ScanNavigator RTE, ScanMaster
executes boundary scan test and on-board programming routines and
can easily be set up to perform conditional looping and branching
operations - a critical feature for program debug and execution
of diagnostic routines. ScanMaster can also be controlled through
DLL calls using test executives such as National Instruments' TestStand
and Teradyne's TestStudio, or through direct API access with language-based
programming.
More Information

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